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W948D6FB / W948D2FB
256Mb Mobile LPDDR
7.6.7 Random Write Cycles
Full-speed random write accesses within a page or pages can be performed as shown in figure below.
CK
CK
Command
Address
WRITE
BA,Col b
WRITE
BA,Col x
WRITE
BA,Col n
WRITE
BA,Col a
WRITE
BA,Col g
NOP
t DQSSmax
DQS
DQ
Di b
Di b ’
Di x
Di x ’
Di n
Di n ’
Di a
Di a ’
DM
1) Dl b etc.= Data in to column b, etc.;
= Don't Care
b ’ , etc.= the next Data In following Dl b, etc. according to the programmed burst order
2) Programmed burst length = 2, 4, 8 or 16 in cases shown. If burst of 4,8 or 16, burst would be truncated
3) Each WRITE command may be to any active bank and may be to the same or different devices.
7.6.8 Write to Read
Data for any Write burst may be followed by a subsequent READ command.
7.6.9 Non-Interrupting Write to Read
To follow a Write without truncating the write burst, t WTR should be met as shown in the figure below.
CK
CK
Command
WRITE
NOP
NOP
NOP
READ
NOP
NOP
Address
BA,Col b
BA,Col n
DQS
DQ
DM
tDQSSmax
DI b
t WTR
CL=3
1) Dl b = Data in to column b
3 subsequent elements of Data In are applied in the programmed order following DI b.
= Don't Care
2) A non-interrupted burst of 4 is shown.
3) t WTR is referenced from the positive clock edge after the last Data In pair.
4) A10 is LOW with the WRITE command (Auto Precharge is disabled)
5) The READ and WRITE commands are to the same device but not necessarily to the same bank.
Publication Release Date : Oct, 15, 2012
- 37 -
Revision : A01-004
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